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MTD10N10EL TMOS E-FETTM Power Field Effect Transistor DPAK for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
Features
VDSS 100 V
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RDS(ON) TYP 0.22
ID MAX 10 A
N-Channel D
* Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Surface Mount Package Available in 16 mm, 13-inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Parameter Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk, L = 1.0 mH, RG =25 ) Thermal Resistance -- Junction to Case -- Junction to Ambient (Note 1) -- Junction to Ambient (Note 2) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 100 100 15 20 10 6.0 35 40 0.32 1.75 -55 to 150 50 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 12 3
G S
Fast Recovery Diode
MARKING DIAGRAM & PIN ASSIGNMENTS
4 4 Drain YWW 10N 10EL 2 1 Drain 3 Gate Source Shipping 75 Units/Rail 2500 Tape & Reel DPAK DPAK Publication Order Number: MTD10N10EL/D
DPAK CASE 369C (Surface Mount) Style 2
10N10EL=Device Code Y = Year WW = Work Week
TJ, Tstg EAS
ORDERING INFORMATION
Device MTD10N10EL MTD10N10ELT4 Package
RJC RJA RJA TL
3.13 100 71.4 260
C/W
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
C
1. When surface mounted to an FR4 board using minimum recommended pad size. 2. When surface mounted to an FR4 board using 0.5 sq in pad size.
(c) Semiconductor Components Industries, LLC, 2004
1
March, 2004 - Rev. 1
MTD10N10EL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 5.0 Adc) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (S Fi (VDS = 80 Vdc, ID = 10 Adc, VGS = 5.0 Vdc) (VDD = 50 Vdc, ID = 10 Adc, VGS = 5.0 Vdc, 5 0 Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. LD -- LS -- 7.5 -- 4.5 -- nH nH ta tb QRR -- -- -- -- 0.98 0.898 124.7 86 38.7 0.539 1.6 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 11 74 17 38 9.3 2.56 4.4 4.66 20 150 30 80 15 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss -- -- -- 741 175 18.9 1040 250 40 pF VGS(th) 1.0 -- RDS(on) VDS(on) -- -- gFS 2.5 1.85 -- 7.9 2.6 2.3 -- mhos -- 1.45 4.0 0.17 2.0 -- 0.22 Vdc mV/C Ohm Vdc V(BR)DSS 100 -- IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc -- 115 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14) (S Fi
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MTD10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20 ID , DRAIN CURRENT (AMPS) TJ = 25C VGS = 10 V 7V 20 5V ID , DRAIN CURRENT (AMPS) 4.5 V 4V 10 3.5 V 5 3V 2V 0 0 1 2 3 4 5 0 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 15 25C 10 TJ = 100C VDS 5 V -55C
15
5
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.35
VGS = 10 V
0.25 TJ = 25C
100C 0.25 TJ = 25C 0.15 -55C
0.2
VGS = 5 V
10 V 0.15
0.05
0
5
10 ID, DRAIN CURRENT (AMPS)
15
20
0.1
0
5
10
15
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
2 VGS = 5 V ID = 5 A 1.5 I DSS , LEAKAGE (nA) 100
Figure 4. On-Resistance versus Drain Current and Gate Voltage
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
VGS = 0 V
TJ = 125C
1
10
100C
0.5
0 - 50
- 25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
150
1 0 20 40 60 80 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTD10N10EL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following:
tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP
where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 Crss Ciss
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
VDS = 0 V
VGS = 0 V
TJ = 25C
Ciss
Coss Crss 10 15 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD10N10EL
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 8 VGS 90 75 60 45 4 Q1 Q2 TJ = 25C ID = 10 A VDS 4 6 8 30 15 0 10 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS 1000 TJ = 25C ID = 10 A VDS = 100 V VGS = 5 V tr tf 10 td(off) td(on)
0
Q3 0 2 QG, TOTAL GATE CHARGE (nC)
t, TIME (ns)
100
1
1
10 RG, GATE RESISTANCE (OHMS)
1
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
10 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C
8
6
4
2 0 0.5
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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MTD10N10EL
SAFE OPERATING AREA
VGS = 20 V SINGLE PULSE TC = 25C EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D , DRAIN CURRENT (AMPS) 50 40 30 ID = 10 A
10 s
10 100 s 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 10 ms dc
20
10 0
0.1 0.1
100
25
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
1
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01
t, TIME (ms)
t1
0.01 0.00001
0.1
1.0
10
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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MTD10N10EL
PACKAGE DIMENSIONS
DPAK CASE 369C-01 ISSUE O
-T- B V R
4 SEATING PLANE
C E
DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MTD10N10EL
E-FET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MTD10N10EL/D

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